The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2026
Filed:
Jul. 04, 2024
Global Unichip Corporation, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Bi-Yang Li, Hsinchu, TW;
Igor Elkanovich, Hsinchu, TW;
Hung-Yi Chang, Hsinchu, TW;
Shih-Cheng Kao, Hsinchu, TW;
Global Unichip Corporation, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
An interface device includes a first controllable delay line (CDL), a first clock generator (CG), a phase detector (PD), a second CDL, and a second CG arranged on a second die. The first CDL delays a source clock signal of a first die to generate a first delayed clock signal. The first CG generates a second delayed clock signal according to the first delayed clock signal. The second CDL delays the source clock signal of the first die to generate a third delayed clock signal. The second CG generates a fourth delayed clock signal according to the third delayed clock signal. Based on a phase difference between a gained clock signal of the first die and the second delayed clock signal detected by the PD, the CDLs adjusts the delay amounts of the source clock signal.