The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

May. 19, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kyle K. Kirby, Eagle, ID (US);

Terrence B. Mcdaniel, Boise, ID (US);

Wei Zhou, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0807 (2013.01); H01L 2224/08123 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80365 (2013.01); H01L 2224/80379 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/04642 (2013.01); H01L 2924/0504 (2013.01); H01L 2924/0554 (2013.01); H01L 2924/059 (2013.01);
Abstract

This document discloses techniques, apparatuses, and systems for semiconductor device interconnects formed through volumetric expansion. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die and the second semiconductor die are bonded at a dielectric layer of the first semiconductor die and a dielectric layer of the second semiconductor die to create one or more interconnect openings. The first semiconductor die includes a reservoir of conductive material located adjacent to the one or more interconnect openings and having a width greater than a width of the one or more interconnect openings. The reservoir of conductive material is heated to volumetrically expand the reservoir of conductive material through the one or more interconnect openings to form one or more interconnects electrically coupling the first semiconductor die and the second semiconductor die. In this way, a connected semiconductor device may be assembled.


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