The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2026
Filed:
Aug. 26, 2022
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Hong Shi, Los Gatos, CA (US);
Li-Sheng Weng, San Diego, CA (US);
Frank Peter Lambrecht, San Jose, CA (US);
Jing Jing, San Jose, CA (US);
Shuxian Wu, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/645 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 24/16 (2013.01); H01L 24/24 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/73209 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/30107 (2013.01);
Abstract
A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.