The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

May. 06, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wei-Cheng Wang, Hsinchu County, TW;

Shih-Hang Chiu, Taichung City, TW;

Kuan-Ting Liu, Hsinchu City, TW;

Chi On Chui, Hsinchu City, TW;

Chia-Wei Chen, Hsinchu, TW;

Jian-Hao Chen, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/7682 (2013.01); H01L 21/7684 (2013.01); H01L 21/76877 (2013.01); H01L 23/53266 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/01 (2025.01); H01L 21/76843 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.


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