The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2026
Filed:
Aug. 31, 2021
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Jungwoo Joh, Allen, TX (US);
Sunglyong Kim, Allen, TX (US);
Seetharaman Sridhar, Richardson, TX (US);
Sameer Pendharkar, Allen, TX (US);
James Craig Ondrusek, Richardson, TX (US);
Srikanth Krishnan, Plano, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/23 (2025.01); H01L 23/482 (2006.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/27 (2025.01); H10D 84/87 (2025.01);
U.S. Cl.
CPC ...
H10D 64/257 (2025.01); H01L 23/4824 (2013.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 62/127 (2025.01); H10D 62/154 (2025.01); H10D 62/158 (2025.01); H10D 64/519 (2025.01); H10D 84/87 (2025.01);
Abstract
An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.