The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Jun. 03, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Te-Yang Lai, Hsinchu, TW;

Hsueh-Ju Chen, Taipei, TW;

Tsung-Da Lin, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 62/118 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01);
Abstract

In an embodiment, a semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and a second dipole dopant. The first dipole dopant along a thickness direction of the first gate dielectric layer has a first concentration peak, and the second dipole dopant along the thickness direction of the first gate dielectric layer has a second concentration peak. The second concentration peak is located between the first concentration peak and an upper surface of the first gate dielectric layer. The second concentration peak is offset from the upper surface of the first gate dielectric layer.


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