Nanosheet epitaxy with full bottom isolation

Abstract

Semiconductor channel layers vertically aligned and stacked one on top of another, separated by a gate stack material wrapping around the semiconductor channel layers, a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the semiconductor channel layers, a horizontal lower surface of the p-FET source drain epitaxy region is adjacent to a horizontal upper surface of an undoped silicon epitaxy. Forming a first stack, second stack and third stack of nanosheet layers on a substrate, each including alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked one on top of another, forming a first sacrificial gate across the first stack, a second sacrificial gate across the second stack and a third sacrificial gate across the third stack, forming an undoped silicon epitaxy between the first and the second stacks and between the second and the third stacks.