The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Sep. 23, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Biju George, Folsom, CA (US);

Zamshed I. Chowdhury, Folsom, CA (US);

Prathamesh Raghunath Shinde, Folsom, CA (US);

Chunhui Mei, San Diego, CA (US);

Fangwen Fu, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2016.01); G06F 12/0862 (2016.01); G06F 12/123 (2016.01);
U.S. Cl.
CPC ...
G06F 12/123 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1021 (2013.01);
Abstract

Prefetch aware LRU cache replacement policy is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (CLs), each including bits for a cache line level (CL level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a CL level to track each CL receiving data, including setting CL level 1 for a CL receiving data in response to a miss in the cache and setting a CL level 2 for a CL receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set CL levels for the CLs.


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