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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12593680 B1

PDFFull Text
Date of Patent:
Mar. 31, 2026

Filed:

Jan. 29, 2021

Integrated assemblies having liners or rings surrounding regions of conductive posts

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

John D. Hopkins, Meridian, ID (US);

Alyssa N. Scarbrough, Boise, ID (US);

Jordan D. Greenlee, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Wells St. John P.S.

Primary Examiner:

Norman D Richards

Assistant Examiner:

Sean Ayers Winters

Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 25/18 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H01L 23/53295 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 23/5226 (2013.01); H01L 25/18 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the first memory region, the intermediate region and the second memory region. The panel is between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the first memory region, the second memory region and the intermediate region, and is directly adjacent the panel. The doped-semiconductor-material is at least part of conductive source structures within the first and second memory regions. Insulative rings surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.

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