The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Apr. 24, 2023
Applicant:

Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, CN;

Inventors:

Xing Wei, Shanghai, CN;

Ziwen Wang, Shanghai, CN;

Rongwang Dai, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/3205 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02532 (2013.01); H01L 21/02381 (2013.01); H01L 21/0242 (2013.01); H01L 21/02422 (2013.01); H01L 21/02428 (2013.01); H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/32055 (2013.01); H01L 21/32105 (2013.01); H01L 21/32134 (2013.01); H01L 21/02013 (2013.01); H01L 21/02019 (2013.01); H01L 21/324 (2013.01);
Abstract

In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 Å, respectively, so as to realize the flatness of the silicon-on-insulator film.


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Wei, Xing. (2026). Method for preparing silicon-on-insulator (U.S. Patent No. 12593626). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12593626

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