The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Jun. 13, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Ching-Ling Lin, Kaohsiung City, TW;

Wen-An Liang, Tainan City, TW;

Chia-Fu Hsu, Tainan City, TW;

Huang-Ren Wei, Tainan City, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 84/014 (2025.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H10D 64/021 (2025.01); H10D 84/0147 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.


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