The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Feb. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hong-Chih Chen, Changhua County, TW;

Ta-Chun Lin, Hsinchu, TW;

Jhon-Jhy Liaw, Zhudong, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/00 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/258 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01);
Abstract

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure penetrates through the first dielectric layer, and a top surface of the gate structure is higher than a top surface of the S/D contact structure.


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Chen, Hong-Chih. (2026). Semiconductor structure including gate spacer layer and dielectric layer having portion lower than top surface of gate spacer layer (U.S. Patent No. 12593489). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12593489

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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