The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2026
Filed:
May. 31, 2023
Analog Devices, Inc., Wilmington, MA (US);
F. Jacob Steigerwald, North Andover, MA (US);
James G. Fiorenza, Carlisle, MA (US);
Guanghai Ding, Bedford, MA (US);
Susan L. Feindt, Andover, MA (US);
Pengfei Wu, Westford, MA (US);
Clifford Alan King, Gloucester, MA (US);
Analog Devices, Inc., Wilmington, MA (US);
Abstract
Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and/or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.