The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Aug. 16, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Sheng-Liang Kuo, Hsinchu, TW;

PO-Yao Lin, Zhudong Township, TW;

Kathy Yan, Hsinchu, TW;

Cooper Yu, Taipei City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/38 (2006.01); H01L 23/42 (2006.01); H10N 10/01 (2023.01); H10N 10/17 (2023.01); H10W 40/22 (2026.01); H10W 40/28 (2026.01); H10W 40/70 (2026.01); H10W 70/02 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 40/28 (2026.01); H10N 10/01 (2023.02); H10N 10/17 (2023.02); H10W 40/22 (2026.01); H10W 40/70 (2026.01); H10W 70/027 (2026.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 74/15 (2026.01); H10W 90/736 (2026.01);
Abstract

Devices and method for forming a chip package assembly, including a package substrate, a fan-out package attached to the package substrate, the fan-out package including a first semiconductor die including a first physical interface and a second semiconductor die including a second physical interface. The chip package assembly further including a heatsink structure including a heatsink base and a cavity within the heatsink base, and a thermoelectric cooler (TEC) embedded within the cavity, wherein the TEC is positioned above the first physical interface and the second physical interface.


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