The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2026
Filed:
Jun. 21, 2023
Applicant:
Apple Inc., Cupertino, CA (US);
Inventors:
Sanjay Dabral, Cupertino, CA (US);
Jun Zhai, Cupertino, CA (US);
Kunzhong Hu, Cupertino, CA (US);
Raymundo M. Camenforte, San Jose, CA (US);
Assignee:
Apple Inc., Cupertino, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 23/585 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16265 (2013.01); H01L 2224/32145 (2013.01);
Abstract
Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.