The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Nov. 12, 2021
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Zhenyang Zhao, Shanghai, CN;

Shiliang Ji, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0338 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01);
Abstract

A semiconductor structure and a method for fabricating the semiconductor structure are provided in the present disclosure. The method includes providing a substrate, wherein the substrate includes a plurality of first regions to-be-etched extending along a first direction; a first region to-be-etched includes a central region and an edge region adjacent to each of two sides of the central region; and a material layer to-be-etched is on the substrate; forming a plurality of discrete initial mask structures on the material layer to-be-etched; etching initial mask structures at the edge region till a surface of the material layer to-be-etched is exposed to form a plurality of mask structures; using the plurality of mask structures as a mask, etching the material layer to-be-etched to form a plurality of discrete layers to-be-etched; and removing layers to-be-etched at the central region till a surface of the substrate is exposed.


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