The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Oct. 25, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Chiang Tsai, Hsinchu City, TW;

Fu-Hsiang Su, Zhubei City, TW;

Ke-Jing Yu, Kaohsiung City, TW;

Chih-Hong Hwang, New Taipei City, TW;

Jyh-Huei Chen, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10D 30/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/62 (2025.01); H01L 21/486 (2013.01); H01L 21/76805 (2013.01); H01L 23/5226 (2013.01); H10D 30/024 (2025.01); H10D 30/6219 (2025.01); H10D 64/511 (2025.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer and first and second gate spacers in first and second openings of the first insulating layer, respectively, forming a first conductive gate stack adjacent to the first gate spacer and forming an insulating material adjacent to the second gate spacer after forming the first conductive gate stack. The method also includes covering the first conductive gate stack and the insulating material with a first insulating capping layer and a second insulating capping layer, respectively, and forming a source/drain contact structure between the first and second gate spacer layers. The top surface of the first insulating layer is higher than those of the insulating material and is substantially level with that of the first conductive gate stack.


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