The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Jan. 27, 2022
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Hsiu-Mei Yu, Hsinchu City, TW;

Guang-Yuan Jiang, Hsinchu City, TW;

Cheng-Yi Hsieh, Jhubei City, TW;

Wei-Chan Chang, Taoyuan City, TW;

Chang-Sheng Lin, Jhunan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H10P 95/00 (2026.01); H10W 20/00 (2026.01); H10W 20/20 (2026.01); H10W 70/40 (2026.01);
U.S. Cl.
CPC ...
H10D 30/471 (2025.01); H10P 95/112 (2026.01); H10W 20/023 (2026.01); H10W 20/20 (2026.01); H10W 70/40 (2026.01);
Abstract

A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 μm. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.


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