The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Jun. 24, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hidehiro Fujiwara, Hsinchu, TW;

Je-Min Hung, Hsinchu, TW;

Haruki Mori, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 3/3562 (2006.01); H03K 19/00 (2006.01); H03K 19/17728 (2020.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 3/3562 (2013.01); H03K 19/0016 (2013.01); H03K 19/17728 (2013.01);
Abstract

A compute-in-memory (CIM) system includes a first leader-follower (L/F) flip-flop (FF), a suspender unit and a multiplication unit. The first L/F FF is configured to receive a data signal. The first L/F FF includes: a first leader FF configured to receive the data signal and a first follower FF configured to generate a signal first_Q_follow that represents a output signal of the first L/F FF. The multiplication unit is configured to receive a weight signal W and the signal first_Q_follow and generate a first product signal. The suspender unit is configured, during a given cycle of the first clock signal, detect that a first scenario is true in which all bits b(k) of the data signal equal logical zero and accordingly suppress latching from being performed by the first L/F FF, and control the multiplication unit to generate the first product signal as being equal to logical zero.


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