The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Jul. 31, 2024
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Cheng-Tung Huang, Kaohsiung City, TW;

Ting-Hao Chang, Kaohsiung City, TW;

Chien-Yu Ko, Tainan City, TW;

Wen-Liang Huang, Taoyuan City, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1693 (2013.01); G11C 11/1697 (2013.01);
Abstract

A pulse signal generator system for a magnetoresistive random access memory includes a delay chain circuit, a NAND gate, an amplitude tunable inverter, and a memory array. The delay chain circuit is used to receive an input signal and generate a delayed output signal. The NAND gate is coupled to the delay chain circuit. The NAND gate includes a first input terminal for receiving the input signal, a second input terminal for receiving the delayed output signal, and an output terminal for outputting a first pulse signal. The amplitude tunable inverter is coupled to the NAND gate. The amplitude tunable inverter includes an input terminal for receiving the first pulse signal, and an output terminal for outputting a second pulse signal. The memory array is coupled to the amplitude tunable inverter.


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