The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Dec. 07, 2022
Applicant:

Jcet Group Co., Ltd., Wuxi City, CN;

Inventors:

Yaojian Lin, Wuxi City, CN;

Danfeng Yang, Wuxi City, CN;

Chen Xu, Wuxi City, CN;

Shuo Liu, Wuxi City, CN;

Chenye He, Wuxi City, CN;

Shasha Zhou, Wuxi City, CN;

Xueqing Chen, Wuxi City, CN;

Assignee:

JCET GROUP CO., LTD., Wuxi City, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 74/47 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 74/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 70/05 (2026.01); H10W 70/093 (2026.01); H10W 70/095 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/012 (2026.01); H10W 74/117 (2026.01); H10W 74/121 (2026.01); H10W 74/15 (2026.01); H10W 74/47 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 70/60 (2026.01); H10W 72/877 (2026.01); H10W 74/00 (2026.01); H10W 90/288 (2026.01); H10W 90/701 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package, an upper package and a first redistribution stack layer disposed between the lower package and the upper package, wherein the first redistribution stack layer is electrically connected to the lower package and the upper package; the lower package includes a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; and the minimum line width/line spacing of the first redistribution stack layer is less than the minimum line width/line spacing of the prefabricated substrate. The lower package includes the prefabricated substrate and the first redistribution stack layer is disposed above the prefabricated substrate and has the minimum line width/line spacing less than that of the prefabricated substrate, so that more chips and/or device packages are integrated in the packaging structure.


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