The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2026
Filed:
Jul. 03, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Ku-Feng Lin, Hsinchu, TW;
Chia-En Huang, Hsinchu, TW;
Chieh Lee, Hsinchu, TW;
Kazumasa Uno, Hsinchu, TW;
Ching-Wei Wu, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/00 (2006.01); G11C 5/06 (2006.01); G11C 17/12 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 20/00 (2023.01); H10B 20/20 (2023.01);
U.S. Cl.
CPC ...
G11C 17/12 (2013.01); G11C 5/063 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 20/20 (2023.02); H10B 20/40 (2023.02);
Abstract
A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.