Hardware processor core having a memory sliced by linear address

Abstract

Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the load address being within a range of address values of that memory slice, a store address buffer to store a store address from the address generation circuit for a store request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the store address being within a range of address values of that memory slice, a store data buffer to store data, including the data for the store request operation that is to be stored at the store address, for each store request operation broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, and a store completion buffer to store the data for the store request operation in response to the store address being stored in the store address buffer of that memory slice, and, in response, clear the store address for the store request operation from the store address buffer and clear the data for the store request operation from the store data buffer.