The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Apr. 08, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Sandro Rossi, Pavia, IT;

Niccolò Brambilla, San Donato Milanese, IT;

Francesco Franco, Milan, IT;

Valeria Bottarel, Novara, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01); H03K 17/06 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2642 (2013.01); H03K 17/063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

According to an embodiment, a circuit for transistor gate stress testing is proposed. The circuit includes a first p-channel MOSFET with its drain linked to the transistor's gate; a second p-channel MOSFET coupling its source to the first p-channel MOSFET's source at a node and its drain to a supply voltage; a first n-channel MOSFET with its source to ground and drain to the transistor's gate; a second n-channel MOSFET with its source to ground and drain to the second p-channel MOSFET's gate; a third p-channel MOSFET with its source and drain bridging the node to the second n-channel MOSFET's drain; a fourth p-channel MOSFET in trans-diode setup, its gate to the third p-channel MOSFET's gate and source to the supply rail; plus a current source placed between the fourth p-channel MOSFET's drain and ground.


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