The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Sep. 23, 2021
Applicant:

Hitachi Energy Ltd, Zürich, CH;

Inventors:

Juergen Schuderer, Zürich, CH;

Chunlei Liu, Oberrohrdorf, CH;

Slavo Kicin, Zürich, CH;

Giovanni Salvatore, Gorizia, IT;

Fabian Mohn, Ennetbaden, CH;

Assignee:

HITACHI ENERGY LTD, Zurich, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49562 (2013.01); H01L 23/3107 (2013.01); H01L 23/3675 (2013.01); H01L 23/49575 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 25/0657 (2013.01); H01L 2224/32258 (2013.01); H01L 2224/49111 (2013.01); H01L 2225/06506 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/1811 (2013.01);
Abstract

The invention relates to a power semiconductor module comprising a conductive base, a conductive top, and at least two power semiconductor devices arranged between the conductive base and the conductive top. The semiconductor devices are each configured for a current of at least 1 A and/or for a voltage of at least 50 V. An insulating spacer layer is arranged on the power semiconductor devices and at least partially between the conductive base and the conductive top. At least two vertical connection elements pass from the power semiconductor devices through the spacer layer and conductively connect the conductive top with the power semiconductor devices. The spacer layer and the vertical connection elements are configured for compensating height differences of the power semiconductor devices.


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