The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jun. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Tien Wu, Taichung, TW;

Wei-Chen Chu, Taichung, TW;

Yu-Chieh Liao, Taoyuan County, TW;

Hsin-Ping Chen, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); G11C 11/412 (2006.01); G11C 11/417 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G11C 11/412 (2013.01); G11C 11/417 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/53252 (2013.01); H10B 10/12 (2023.02);
Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first interconnect layer over a substrate, the first interconnect layer including a first conductive feature and a second conductive feature, forming a patterned mask on the first interconnect layer, one or more openings in the patterned mask overlaying the second conductive feature, recessing the second conductive feature through the one or more openings in the patterned mask, and forming a second interconnect layer over the first interconnect layer. The second interconnect layer includes a first via in contact with the first conductive feature and a second via in contact with the second conductive feature.


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