The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jul. 12, 2023
Applicant:

Invention and Collaboration Laboratory Pte. Ltd., Singapore, SG;

Inventors:

Chao-Chun Lu, Taipei City, TW;

Ming-Hong Kuo, Hsinchu, TW;

Chun-Nan Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/34 (2023.02); H10B 12/053 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02);
Abstract

A memory structure includes a semiconductor substrate, an active region, a transistor, and a buried-WL (word line). The semiconductor substrate has an original semiconductor surface. The active region is in the semiconductor substrate and surrounded by a shallow trench isolation (STI) region. The transistor is formed based on the active region. The buried-WL (word line) extends through the active region and the STI region. The buried-WL has variable depth or width along the extension direction of the buried-WL.


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Lu, Chao-Chun. (2026). Memory structure having a buried word line (U.S. Patent No. 12575084). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12575084

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