The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Sep. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Hua-Hsin Yu, Hsinchu, TW;

Che-An Lee, Hsinchu, TW;

Hau-Tai Shieh, Hsinchu, TW;

Cheng Hung Lee, Hsinchu, TW;

Hung-Jen Liao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G11C 29/46 (2006.01); G11C 29/54 (2006.01);
U.S. Cl.
CPC ...
G11C 29/46 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 29/54 (2013.01);
Abstract

An input/output circuit comprises a bypass circuit, a first latch, a second latch, a first transistor, and a second transistor. The bypass circuit is configured to directly receive a data signal and indirectly receive a write enable signal. The first latch is coupled between a first data line and a second data line. The second latch is operatively coupled to the first latch and configured to generate a data output signal based on a voltage level presented on the second data line. The first transistor is coupled to the first latch and gated by a sense enable signal. The second transistor is coupled to the first latch and gated by a clock signal. The first transistor and the second transistor are alternately activated in each of a plurality of operation modes of the input/output circuit.


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