The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2026
Filed:
Apr. 24, 2023
Intel Corporation, Santa Clara, CA (US);
Subramaniam Maiyuran, Gold River, CA (US);
Durgaprasad Bilagi, Folsom, CA (US);
Joydeep Ray, Folsom, CA (US);
Scott Janus, Loomis, CA (US);
Sanjeev Jahagirdar, Folsom, CA (US);
Brent Insko, Portland, OR (US);
Lidong Xu, Beijing, CN;
Abhishek R Appu, El Dorado Hills, CA (US);
James Holland, Folsom, CA (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
Nikos Kaburlasos, Folsom, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Xinmin Tian, Union City, CA (US);
Guei-Yuan Lueh, San Jose, CA (US);
Changliang Wang, Bellevue, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a state of multiple intellectual property (IP) cores that have access to a common cache via a central fabric is observed. Responsive to the observed state being indicative of performance of a standalone workload by a first IP core of the multiple IP cores, the common cache is treated as a local cache of the first IP core by powering off the central fabric and causing the first IP core to access the common cache via a low power access path between the first IP core and the common cache that is outside of the central fabric.