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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12571971 B1

PDFFull Text
Date of Patent:
Mar. 10, 2026

Filed:

Apr. 01, 2025

Converting processing dimensions of a wafer package

Applicant:

Celestial Ai Inc., Santa Clara, CA (US);

Inventors:

Ankur Aggarwal, Pleasanton, CA (US);

Anmol Rathi, San Jose, CA (US);

Suresh Venkata Pothukuchi, Chandler, AZ (US);

Assignee:

Celestial AI Inc., Santa Clara, CA (US);

Attorneys:

Ray Quinney & Nebeker P.C.

James S. Bullough

Primary Examiner:

Kaveh C Kianni

Int. Cl.
CPC ...
G02B 6/43 (2006.01); G02B 6/12 (2006.01); G02B 6/13 (2006.01); G02B 6/42 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/16 (2023.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01); H10D 80/30 (2025.01); H10F 55/00 (2025.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G02B 6/4239 (2013.01); G02B 6/12004 (2013.01); G02B 6/13 (2013.01); G02B 6/42 (2013.01); G02B 6/4215 (2013.01); G02B 6/4228 (2013.01); G02B 6/4243 (2013.01); G02B 6/4246 (2013.01); G02B 6/4249 (2013.01); G02B 6/4251 (2013.01); G02B 6/4255 (2013.01); G02B 6/4256 (2013.01); G02B 6/4259 (2013.01); G02B 6/4274 (2013.01); G02B 6/4278 (2013.01); G02B 6/428 (2013.01); G02B 6/4292 (2013.01); G02B 6/4293 (2013.01); G02B 6/4295 (2013.01); G02B 6/43 (2013.01); H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 23/315 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/5384 (2013.01); H01L 25/165 (2013.01); H01L 25/167 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 80/00 (2023.02); H10D 80/30 (2025.01); H10F 55/00 (2025.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1436 (2013.01);
Abstract

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing wafers having circuit packages formed thereon. Techniques described herein related to modifying a dimension of wafers in order that the wafers conform to a nominal dimension, such that the wafers may be implemented in connection with processing equipment that is specifically configured to operate on wafers of the nominal dimension.

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