The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2026
Filed:
Jun. 06, 2023
Applicant:
Walton Advanced Engineering, Inc., Kaohsiung, TW;
Inventors:
Assignee:
WALTON ADVANCED ENGINEERING, INC., Kaohsiung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3192 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/3135 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 23/293 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/1302 (2013.01);
Abstract
A chip package and a method of manufacturing the same are provided. The chip package includes at least one insulating protective layer disposed on a periphery of a surface of a seed layer correspondingly. A plurality of insulating protective layers is arranged at the seed layer of a plurality of rectangular chips of a wafer and located corresponding to a plurality of dicing streets. Thereby cutting tools only cut the insulating protective layer, without cutting a thick metal layer during cutting process. The insulating protective layer is formed on a periphery of the thick metal layer of the chip package after the cutting process.