The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2026
Filed:
Mar. 07, 2023
Applicant:
Panjit International Inc., Kaohsiung City, TW;
Inventors:
Chung-Hsiung Ho, Kaohsiung City, TW;
Wen-Liang Huang, Kaohsiung City, TW;
Jeng-Sian Wu, Taoyuan City, TW;
Assignee:
PANJIT INTERNATIONAL INC., Kaohsiung City, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 24/05 (2013.01); H10D 62/117 (2025.01); H01L 24/03 (2013.01); H01L 24/95 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/0381 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/95001 (2013.01);
Abstract
A wafer-level-package device with peripheral side wall protection has a die, multiple conductive bumps, and a protection layer. The die has a top surface, a bottom surface, and a peripheral side wall. A cavity is formed on the peripheral side wall of the die and around the die. The multiple conductive bumps are mounted on at least one of the top surface and the bottom surface of the die. The protection layer covers the die, the cavity, and the multiple conductive bumps. The multiple conductive bumps are exposed from the protection layer.