The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Feb. 04, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Jingjing Chen, San Jose, CA (US);

Ming-Yeh Chuang, McKinney, TX (US);

Guruvayurappan Mathur, Allen, TX (US);

James Todd, Plano, TX (US);

Ronald Chin, Dallas, TX (US);

Thomas Lillibridge, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/658 (2025.01); H10D 30/0215 (2025.01); H10D 64/257 (2025.01); H10D 64/513 (2025.01);
Abstract

The present disclosure generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate, a dielectric oxide layer, and a field oxide region. The semiconductor substrate has a top surface. The dielectric oxide layer is over the top surface of the semiconductor substrate. The field oxide region is over the semiconductor substrate. The field oxide region is connected to the dielectric oxide layer through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate. In a cross-section along a direction from the field oxide region to the dielectric oxide layer, the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate.


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