The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2026
Filed:
May. 31, 2023
Pakal Technologies, Inc., San Francisco, CA (US);
Paul M. Moore, Hillsboro, OR (US);
Vladimir Rodov, Seattle, WA (US);
Pakal Technologies, Inc., San Francisco, CA (US);
Abstract
A method of forming a layered, high power vertical insulated-gate switch uses an n-type substrate. A p-well is formed by implantation in the top surface of the substrate followed by implanting n-type dopants in the p-well to form n+ source regions. Trenched gates are formed extending through the n+ source regions and into the p-well. The wafer is transferred to a carrier and the bottom surface of the wafer substrate is thinned by CMP. An n-buffer layer is then epitaxially grown on the bottom surface using low temperature epitaxy (LTE). The low temperature does not substantially diffuse the dopants in the overlying regions. A bottom p+ layer is then formed by LTE. Anode and cathode metal electrodes are then formed. The n-buffer layer and p+ layers can be precisely formed for optimal efficiency and the LTE maintains the dopant profiles of the overlying regions.