The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Jul. 31, 2024
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc China Company, Limited, Shanghai, CN;

Inventors:

Yaqi MA, Hsinchu, TW;

Lei Pan, Hsinchu, TW;

Junkui Hu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); G06F 30/392 (2020.01); H03K 3/356 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); G06F 30/392 (2020.01); H03K 3/35613 (2013.01); H03K 19/0185 (2013.01); H10D 84/85 (2025.01);
Abstract

A method of generating an integrated circuit (IC) layout diagram includes defining first through fourth PMOS transistors in an n-well region, arranging a plurality of conductive regions whereby a bias circuit is configured to include the first and second PMOS transistors and a level shifter is configured to include the third and fourth PMOS transistors, and arranging a plurality of conductive elements whereby a first power domain includes electrical connections to each of the first and third PMOS transistors and a second power domain includes electrical connections to each of the second and fourth PMOS transistors.


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