logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12564031 B1

PDFFull Text
Date of Patent:
Feb. 24, 2026

Filed:

Dec. 19, 2022

Semiconductor device and method for manufacturing same

Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Zhaohui Tang, Wuhan, CN;

Lei Zhang, Wuhan, CN;

Yuting Zhou, Wuhan, CN;

Si Qiao, Wuhan, CN;

Assignee:

YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan, CN;

Attorney:

BAYES PLLC

Primary Examiner:

Richard A Booth

Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76819 (2013.01); H01L 21/0214 (2013.01); H01L 21/02178 (2013.01); H01L 21/02186 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/68 (2025.01); H10D 30/6891 (2025.01); H10D 30/69 (2025.01); H10D 30/694 (2025.01); H10D 64/017 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01); H10B 41/35 (2023.02); H10B 43/35 (2023.02);
Abstract

A method for manufacturing a semiconductor device is provided. The method includes the following. A substrate is provided. A stacked structure is formed on the substrate. The stacked structure includes first material layers and gate layers that are alternatively stacked. The stacked structure includes a giant block (GB) region and a stair-step region. A third material layer is formed on an upper surface of the GB region and an upper surface of the stair-step region. A fourth material layer filling the stair-step region and covering the GB region is formed. At least one contact structure is located in the stair-step region. Each of the at least one contact structure penetrates the third material layer and is connected with a respective one of the gate layers.

Find Patent Forward Citations

Tang, Zhaohui. (2026). Semiconductor device and method for manufacturing same (U.S. Patent No. 12564031). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12564031

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…