The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Feb. 22, 2023
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Takashi Yoshimura, Matsumoto, JP;

Makoto Shimosawa, Matsumoto, JP;

Motoyoshi Kubouchi, Matsumoto, JP;

Misaki Uchida, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/62 (2025.01); H01L 21/22 (2006.01); H01L 21/285 (2006.01); H10D 12/00 (2025.01); H10D 62/53 (2025.01); H10D 64/00 (2025.01); H10D 84/60 (2025.01);
U.S. Cl.
CPC ...
H10D 64/62 (2025.01); H01L 21/221 (2013.01); H01L 21/28518 (2013.01); H10D 12/481 (2025.01); H10D 62/53 (2025.01); H10D 64/117 (2025.01); H10D 84/617 (2025.01);
Abstract

Provided is a semiconductor device including a MOS gate structure provided in a semiconductor substrate, including: an interlayer dielectric film which includes a contact hole and is provided above the semiconductor substrate; a conductive first barrier metal layer provided on side walls of the interlayer dielectric film in the contact hole; a conductive second barrier metal layer stacked on the first barrier metal layer in the contact hole; and a silicide layer provided on an upper surface of the semiconductor substrate below the contact hole, in which the first barrier metal layer is more dense than the second barrier metal layer, and a film thickness thereof is 1 nm or more and 10 nm or less.


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