Method for fabricating fully depleted silicon-on-insulator pmos devices

Abstract

The present application discloses a method for fabricating fully depleted silicon-on-insulator PMOS devices, the method includes sequentially forming a polysilicon layer and a hard mask oxide layer on an FDSOI substrate structure; etching to a SiGe layer by using the hard mask oxide layer as a mask to form a PMOS gate stack structure; sequentially depositing a spacer dielectric layer and an epitaxial hard mask; performing photolithography and etching to remove the epitaxial hard mask above the PMOS gate stack and thin the spacer dielectric layer; performing in situ photo resist strip; and etching to remove a residual spacer dielectric layer above the PMOS gate and on its surrounding substrate. The present application can effectively reduce the accumulative loss of a SiGe substrate after the epitaxial hard mask etching, improving the epitaxial growth of PMOS regions and ensuring the performance of the fabricated fully depleted silicon-on-insulator PMOS devices.