The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Dec. 22, 2021
Applicant:

Intel Ndtm Us Llc, Santa Clara, CA (US);

Inventors:

Deepak Thimmegowda, Fremont, CA (US);

Chang Wan Ha, San Ramon, CA (US);

MD Rezaul Karim Nishat, Santa Clara, CA (US);

Liu Liu, Dalian, CN;

Yuanrong Shui, Dalian, CN;

Kwame Eason, East Palo Alto, CA (US);

Ahmed Reza, San Jose, CA (US);

Hoon Koh, San Jose, CA (US);

Assignee:

Intel NDTM US LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/20 (2023.01); G11C 8/14 (2006.01); G11C 16/04 (2006.01); H01L 23/48 (2006.01); H10B 41/10 (2023.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/20 (2023.02); G11C 8/14 (2013.01); G11C 16/0483 (2013.01); H01L 23/481 (2013.01); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02);
Abstract

Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.


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