The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Jul. 18, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jonathan D. Harms, Boise, ID (US);

David Hulton, Boise, ID (US);

Jeremy Chritz, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/406 (2006.01); G06F 11/10 (2006.01); G11C 29/02 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 11/406 (2013.01); G06F 11/1052 (2013.01); G11C 29/02 (2013.01); G11C 29/52 (2013.01); G11C 2211/4062 (2013.01);
Abstract

Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.


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