The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Oct. 27, 2022
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Shenzhen Sts Microelectronics Co., Ltd., Shenzhen, CN;

Inventors:

Yi Ming Liang, Shenzhen, CN;

Roberto Tiziani, Nerviano, IT;

Qian Liu, Shenzhen, CN;

Feng Ding, Shenzhen, CN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/373 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 23/13 (2013.01); H01L 23/3735 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 2224/29111 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/8384 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15159 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/152 (2013.01);
Abstract

Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips. Embodiments of the present disclosure may at least simplify the double-sided heat dissipation structure and improve the heat dissipation effect of the chip.


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