logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12557627 B1

PDFFull Text
Date of Patent:
Feb. 17, 2026

Filed:

Aug. 18, 2023

Stacked fet with bottom epi size control and wraparound backside contact

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Jay William Strane, Wappingers Falls, NY (US);

Shay Reboh, Guilderland, NY (US);

Brent A. Anderson, Jericho, VT (US);

Junli Wang, Slingerlands, NY (US);

Albert M. Chu, Nashua, NH (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Tutunjian & Bitetto, P.C

L. Jeffrey Kelly

Primary Examiner:

Ajay Arora

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

Find Patent Forward Citations

Xie, Ruilong. (2026). Stacked fet with bottom epi size control and wraparound backside contact (U.S. Patent No. 12557627). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12557627

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…