The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Feb. 03, 2023
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Sachin Shrivastava, Noida, IN;

Deepak Karnatak, Ghaziabad, IN;

Vishal Rastogi, Noida, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 1/80 (2012.01); G03F 7/20 (2006.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G03F 7/00 (2006.01); G06F 115/12 (2020.01); G06F 119/02 (2020.01); G06F 119/18 (2020.01); G06F 119/22 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01); G03F 1/80 (2013.01); G03F 7/20 (2013.01); G03F 7/70653 (2023.05); G03F 7/70681 (2023.05); G06F 2115/12 (2020.01); G06F 2119/02 (2020.01); G06F 2119/18 (2020.01); G06F 2119/22 (2020.01);
Abstract

Various embodiments provide for inserting an etching shape in a circuit design based on one or more spacing rules, which can be part of electronic design automation (EDA). Some embodiments described herein address wire-end spacing violations for abutted cell placements by enabling one or more etching shapes to be inserted during block implementations, without needing to insert the etching shape at a top level of a circuit design. Additionally, some embodiments described herein address violations of one or more height rules by supporting variable trim height while ensuring that no new violation is introduced with a new etching shape.


Find Patent Forward Citations

Shrivastava, Sachin. (2026). Etching shape insertion based on spacing rule (U.S. Patent No. 12554917). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12554917

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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