The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Jun. 03, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Han Wang, Hsinchu, TW;

Yu-Ting Lin, Hsin-Chu, TW;

Chia Hong Lin, Hsinchu County, TW;

Kao Chih Liu, Changhua County, TW;

Wei-Cheng Liu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/48 (2006.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); H01L 21/76898 (2013.01); H01L 23/5283 (2013.01); H01L 23/481 (2013.01); H10D 84/83 (2025.01); H10D 84/834 (2025.01);
Abstract

An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.


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