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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12550734 B1

PDFFull Text
Date of Patent:
Feb. 10, 2026

Filed:

Apr. 01, 2022

Integrated circuit package and method

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jiun Yi Wu, Zhongli, TW;

Chen-Hua Yu, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Christine S Kim

Assistant Examiner:

Sesha Sairaman Srinivasan

Int. Cl.
CPC ...
H01L 23/433 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/4334 (2013.01); H01L 21/4871 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a metal-to-metal bond and a heat dissipation feature over the first die. The heat dissipation feature includes a thermal base over the first die and surrounding the second die, wherein the thermal base is made of a metal; and a plurality of thermal vias on the thermal base; and an encapsulant over first die and surrounding the second die, surrounding the thermal base, and surrounding the plurality of thermal vias.

Find Patent Forward Citations

Wu, Jiun. (2026). Integrated circuit package and method (U.S. Patent No. 12550734). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12550734

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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