The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jul. 15, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Hemanth Jagannathan, Niskayuna, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Juntao Li, Cohoes, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/025 (2025.01); H10D 30/63 (2025.01); H10D 64/252 (2025.01); H10D 84/013 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/016 (2025.01); H10D 84/038 (2025.01);
Abstract

Embodiments of present invention provide a transistor structure. The transistor structure includes a first vertical fin of a first vertical transistor, the first vertical fin having a first and a second sidewall and a first and a second vertical end; a first bottom source/drain (S/D) region underneath the first vertical fin, wherein the first bottom S/D region having an edge that vertically aligns with the first vertical end of the first vertical fin; and a first gate stack surrounding the first vertical fin, wherein the first bottom S/D region horizontally extends beyond the first vertical fin, except at the edge of the first bottom S/D region that vertically aligns with the first vertical end of the first vertical fin, to have at least a portion vertically underneath the first gate stack. A method of manufacturing the transistor structure is also provided.


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