The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jun. 02, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Su Chen Fan, Cohoes, NY (US);

Dominik Metzler, Clifton Park, NY (US);

Hemanth Jagannathan, Niskayuna, NY (US);

Jing Guo, Fremont, CA (US);

Jay William Strane, Warwick, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H10D 84/83 (2025.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H10D 86/441 (2025.01); H10D 86/451 (2025.01); H10D 86/60 (2025.01);
Abstract

A semiconductor structure including a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor, where at least one vertical surface of the first top contact is substantially flush with at least one vertical surface of the isolation region, and where at least one vertical surface of the second top contact is substantially flush with the at least one vertical surface of the isolation region.


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