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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12550328 B1

PDFFull Text
Date of Patent:
Feb. 10, 2026

Filed:

Jul. 17, 2023

Three-dimensional memory device including a mid-stack source layer and methods for forming the same

Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Naohiro Hosoda, Yokkaichi, JP;

Kazuki Isozumi, Yokkaichi, JP;

Masanori Tsutsumi, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:

THE MARBURY LAW GROUP PLLC

Primary Examiner:

Thanh Y Tran

Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02); H10B 80/00 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a vertical semiconductor channel that extends through the first-tier alternating stack, the source layer, and the second-tier alternating stack. The vertical semiconductor channel has sidewall in contact with the source layer.

Find Patent Forward Citations

Hosoda, Naohiro. (2026). Three-dimensional memory device including a mid-stack source layer and methods for forming the same (U.S. Patent No. 12550328). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12550328

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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