The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Jun. 29, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Qixin Shen, Sunnyvale, CA (US);

Chuanxi Yang, Los Altos, CA (US);

Hang Yu, San Jose, CA (US);

Deenesh Padhi, Sunnyvale, CA (US);

Gill Yong Lee, San Jose, CA (US);

Sung-Kwan Kang, San Jose, CA (US);

Abdul Wahab Mohammed, Santa Clara, CA (US);

Hailing Liu, Union City, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/033 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/02304 (2013.01); H01L 21/0217 (2013.01); H01L 21/02211 (2013.01); H01L 21/02274 (2013.01); H01L 21/02315 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H10B 12/30 (2023.02);
Abstract

Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.


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