The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Aug. 09, 2022
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Mark I. Gardner, Cedar Creek, TX (US);

H. Jim Fulford, Marianna, FL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/01 (2025.01); H01L 21/762 (2006.01); H10D 86/00 (2025.01);
U.S. Cl.
CPC ...
H10D 86/01 (2025.01); H01L 21/76251 (2013.01); H10D 86/201 (2025.01);
Abstract

A method of fabricating a semiconductor device includes receiving a first wafer including a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer. The first SOI stack includes a first semiconductor. A second wafer is received that includes a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer. The second SOI stack includes a second semiconductor. The front side of the first wafer is bonded to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer. The second substrate is removed. A stack of transistor devices is formed with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.


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